Semiconductor devices, such as BGA semiconductor packages or card type semiconductor devices, generally utilize a substrate serving as electrical interconnection for chip, wherein the substrate has a plurality of outer pads able to directly serve as external contact electrodes or connecting external terminals, such as tin balls or metal pins. In order to match a predetermined socket specification, the location and electrical functions of the outer pads of substrate cannot be changed, however there still are different serial arrangements in bonding pads of chips according to various designations or/and manufactures of wafer for even the semiconductor chip with same electrical functions. Therefore, while serial arrangement of bonding pads of chip is once changed resulting in a problem that original substrate is no longer applied for different chip, it is necessary to design or replace another substrate having corresponding wiring pattern for application so that substrate variety will be increased without limitation. Besides, the lead time for manufacturing substrate also becomes longer.
Referring to FIG. 1, a semiconductor device, such as a memory card, mainly comprises a substrate 100, a chip 10, a plurality of bonding wires 30 and a molding compound 40. As shown in FIG. 2, the substrate 100 has a plurality of inner pads 111, 112 and 113, a plurality of outer pads 121, 122 and 123, a plurality of wirings 130 and a plurality of plated through holes 140 or electrical vias. The inner pads 111, 112 and 113 are disposed on an upper surface 101 of the substrate 100 and the outer pads 121, 122 and 123 are disposed on a lower surface 102 of the substrate 100. The inner pads 111, 112 and 113 are electrically connected to the corresponding outer pads 121, 122 and 123 through a controller (not shown in figures) by the wirings 130 and the plated through holes 140. The chip 10 is disposed on the upper surface 101 of the substrate 100 and has a plurality of bonding pads arranged from up to down in order of CP1, CP2 and CP3 as shown in FIG. 2, wherein the bonding pads CP1, CP2 and CP3 are electrically connected to the inner pads 111, 112 and 113 respectively by a plurality of bonding wires 30. The molding compound 40 is formed on the upper surface 101 of the substrate 100 to encapsulate the chip 10 and the bonding wires 30.
Referring to FIG. 2, the inner pads are numbered as a first inner pad 111, a second inner pad 112 and a third inner pad 113 in turn and the outer pads are numbered as a first outer pad 121, a second outer pad 122 and a third outer pad 123 in turn. Also, the bonding pads CP1, CP2 and CP3 are numbered as a first bonding pad CP1, a second bonding pad CP2 and a third bonding pad CP3 according to their serial arrangement and functions. Referring to FIG. 2 again, the first bonding pad CP1 is electrically connected to the first inner pad 111 by the bonding wire 30 in order to electrically connect to the first outer pad 121 via the wiring 130 and PTH 140. Similarly, the second bonding pad CP2 is electrically connected to the second inner pad 112 by wire-bonding in order to electrically connect to the second outer pad 122, and the third bonding pad CP3 is electrically connected to the third inner pad 113 by wire-bonding in order to electrically connect to the third outer pad 123.
Referring to FIG. 3, when another chip 20 has a different serial arrangement of bonding pads arranged in order of the second bonding pad CP2, the third bonding pad CP3 and the first bonding pad CP1 from up to down, in order to match a same product socket that the first bonding pad CP1 is still needed to be electrically connected to the first outer pad 121 at the same location of substrate 100. Similarly, the second bonding pad CP2 is also needed to be electrically connected to the second outer pad 122 at the same location of substrate 100 and the third bonding pad CP3 is also needed to be electrically connected to the third outer pad 123 at the same location of substrate 100. The original substrate 100 is no longer applied for the chip 20 having different serial arrangement of bonding pads so that it is necessary to design and manufacture another known exclusive substrate 200 which includes a plurality of inner pads 211, 212 and 213, a plurality of outer pads 221, 222 and 223, a plurality of wirings 230 and a plurality of plated through holes 240. According to different serial arrangement of bonding pads, the exclusive substrate 200 has a different inner wiring layout from the foregoing original substrate 100. As shown in FIG. 3, the first outer pad 221 is electrically connected to the third inner pad 213 by proper wiring 230 and PTH 240, the second outer pad 222 electrically connected to the first inner pad 211 and the third outer pad 223 electrically connected to the second inner pad 212. When manufacturing a semiconductor device, the bonding wires 30 are formed to electrically connect the third inner pad 213 to the first bonding pad CP1, the first inner pad 211 to the second bonding pad CP2 and the second inner pad 212 to the third bonding pad CP3. By means of modifying the inner wiring pattern of substrate, the ultimate purpose that the first outer pad 221 is electrically connected to the first bonding pad CP1 of the chip 20, the second outer pad 222 is electrically connected to the second bonding pad CP2 of the chip 20 and the third outer pad 223 is electrically connected to the third bonding pad CP3 of the chip 20 can be achieved. Therefore, while the serial arrangement of the bonding pads of chip is changed, it tends to replace or remanufacture another substrate 20 with different wiring pattern that results in increasing substrate variety and widely prolongs lead time for manufacturing substrate to be disadvantageous in sample manufacture and small quantity production.